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A new hardware leak suggests that Advanced Micro Devices is preparing a notable internal redesign for its next desktop and server CPU generation. According to information first reported by Tom’s Hardware, a well-known leaker claims that AMD’s upcoming Zen 6 processors will use 48MB of L3 cache per core complex die, while increasing the number of cores per CCD to twelve.
The key point behind the rumor is not only the larger cache capacity. The more important design signal is that AMD appears to be preserving the same L3 cache-to-core ratio used in Zen 5, even as it raises core density inside each CCD.
What the leak actually claims
The information comes from hardware leaker HXL, who shared early details on Zen 6 CCD configuration. The claim states that:
- Each Zen 6 CCD will contain 12 CPU cores
- Each CCD will also include 48MB of shared L3 cache
- The effective cache per core remains 4MB per core, matching Zen 5
For reference, Zen 5 uses an eight-core CCD with 32MB of L3 cache. Dividing the cache evenly, both generations land at the same cache density per core. This strongly suggests that AMD wants to avoid reducing cache availability as it pushes core counts higher.
Why AMD may be keeping the cache ratio unchanged
L3 cache plays a critical role in modern CPU performance. It acts as a high-speed buffer between system memory and individual cores, helping reduce memory latency and improving data sharing between threads.
When manufacturers increase the number of cores without scaling cache capacity, performance can suffer in workloads that rely heavily on shared data access. Gaming, real-time simulation, and mixed productivity workloads often show sensitivity to L3 cache size and access behavior.
By scaling L3 cache proportionally with the new 12-core CCD layout, AMD appears to be prioritizing consistency and predictability across performance profiles rather than chasing raw core counts alone.
This design approach also fits AMD’s recent strategy. In recent Zen generations, the company focused on improving real-world performance per core and memory behavior rather than simply expanding theoretical compute throughput.
A larger CCD is likely part of the design
The leak also points toward a modest increase in the physical size of the Zen 6 CCD. With four additional cores and 16MB more L3 cache compared to Zen 5, the silicon footprint would naturally grow.
This is notable because AMD kept CCD sizes relatively stable across multiple past Zen generations, even when internal logic changed. A larger CCD may reflect:
- Higher transistor density targets
- A more complex front-end and execution pipeline
- Expanded cache structures and routing
While the exact die size remains unconfirmed, the reported changes strongly indicate that Zen 6 is not a minor revision.
What 12 cores per CCD really means
Moving from eight cores per CCD to twelve is a significant architectural change. AMD’s chiplet strategy depends heavily on balancing performance, power, and yield across multiple small dies.
A higher core density per CCD can deliver several advantages:
- Fewer CCDs may be required to reach high core counts
- Inter CCD communication overhead can be reduced
- Platform scalability becomes simpler for workstation and server parts
However, it also introduces new challenges:
- Thermal density inside each CCD increases
- Scheduling and internal fabric traffic become more complex
- Cache access behavior must remain tightly optimized
The decision to scale L3 cache proportionally suggests AMD is already accounting for these challenges.
The bigger picture
If the leak proves accurate, Zen 6 represents a more structural evolution than a simple generational refresh.
The rumored highlights can be summarized clearly:
- 12 cores per CCD
- 48MB L3 cache per CCD
- Unchanged cache-to-core ratio compared with Zen 5
- Likely larger and more complex CCD design
- Expected use of an advanced manufacturing node
For enthusiasts and professional users alike, this approach signals that AMD is preparing Zen 6 as a platform that can scale higher without sacrificing memory behavior or real-world responsiveness. As official disclosures begin to surface, L3 cache scaling may become one of the most important architectural stories of the next Ryzen generation.
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